Method and apparatus for enabling global compiler optimizations in the presence of exception handlers within a computer program
US5778233A · kind A · utility
40Cited by
14References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1996 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Oct 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus allows a compiler to optimize code in the presence of exception handlers. According to a first embodiment, arcs are added to a control flow graph, prior to performing global optimizations, to account for exception handling code. According to the second embodiment, information relating to control flow to exception handlers is provided in pseudo-references in the code, which allows the compiler to determine how to appropriately optimize the code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.