Performance enhancing memory interleaver for data frame processing
US5778414A · kind A · utility
59Cited by
1References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1996 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Jun 13, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is a frame processing engine for receiving and processing a data frame having a header and a payload, comprising a first memory for receiving at least a portion of the header of the data frame; a second memory for receiving the payload of the data frame; and a controller, upon receipt of the data frame, for storing the header (at least most of it) in the first memory and the remainder of the data frame (including the payload) in the second memory, with the first memory having a shorter access time than the second memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.