Parallel process address generator and method
US5778416A · kind A · utility
29Cited by
16References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1997 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Apr 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory linked address generator and method for a complex arithmetic processor executing an algorithm sequence includes memories, a clock for generating a clock cycle, and a decoder for determining position of the complex arithmetic processor within the algorithm sequence. The decoder is coupled to the clock and address pointer generators are coupled to the decoder and to the memories. The address pointer generators generate address pointers within the clock cycle for at least some of the memories in response to the position of the complex arithmetic processor within the algorithm sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.