DRAM with high bandwidth interface that uses packets and arbitration
US5778419A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1996 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Feb 23, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates. The memory chip includes a memory device and an interface capable of achieving high bandwidth throughput. The memory device decodes, arbitrates between, and executes memory access commands, and generates memory access responses. The interface includes a data path, and a number of memory controllers. The interface receives and transmits input and output data streams, and the memory controllers control the flow of the input and output data streams within the memory chip. A packet buffer is coupled between the data path and the memory device. The packet buffer provides for temporary storage of memory access commands, response information, and forwarding data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.