Distributed placement, variable-size cache architecture
US5778424A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 1993 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Apr 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distributed variable-size cache placement architecture includes plural cache storage units (CSUs), each of which includes a CSU control logic, an address director, a data director, a placement array, placement logic (i.e., distribution controller), and a set associative memory for caching data. All CSUs in the architecture are connected over a communication network to a single processor interface and mainstore and which provides information to all CSUs about the status of each of the other CSUs. Any number of CSUs may be connected in parallel to provide a variable size cache. All CSUs sharing a processor interface utilize the same placement block size, contain the same number of sets of cache elements and use the same CSU placement mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.