Programmable high performance mode for multi-way associative cache/memory designs
US5778428A · kind A · utility
9Cited by
15References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1995 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Dec 22, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides circuitry which facilitates user selection of alternative memory accessing techniques. The present invention provides a design approach or technique to transform the time associated with waiting for a valid "way-select" signal into cycle reduction time, thus providing a beneficial increase in the overall performance of multi-way associative cache and memory designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.