Method for fabricating a semiconductor memory cell in a DRAM
US5780339A · kind A · utility
47Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 1997 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | May 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
This present invention is a method of fabricating a semiconductor memory cell in a DRAM. This invention utilizes a inter plug technique and nitride sidewall spacers to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, the method of this invention allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.