Reduced output swing with p-channel pullup diode connected
US5781034A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Jul 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer having a reduced-swing output includes a p-channel pullup transistor as the primary pullup device. A biasing circuit is provided so as to bias the gate terminal of the pullup p-channel transistor to a predetermined level. The predetermined level is effective to cause the p-channel pullup transistor to shut off when the output of the buffer reaches a reduced magnitude output level (V.sub.OH). In the disclosed embodiment, the biasing circuit includes an n-channel transistor connected between the gate and drain terminals of the p-channel pullup transistor. The biasing circuit also includes a p-channel transistor having a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the pullup transistor. When the output of the buffer is desired to be in a logic high state, both of the biasing transistors are "ON." The voltage applied to the gate of the pullup transistor is, in effect, the result of the voltage divider effect between the "ON" resistances of the two biasing transistors. These transistors divide the voltage between V.sub.cc and the voltage on the drain of the pullup transistor. A third p-channel transistor is provided, and which ha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.