High speed phase locked loop test method and means
US5781038A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Feb 5, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.