Dual push-pull amplifier circuit and method
US5781072A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Sep 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier circuit (30) has the capability for driving a large number of loads while still maintaining the desirable gain response. The amplifier circuit (30) includes two push-pull amplifier circuits (31 and 41). A first push-pull amplifier circuit (31) has a pair of bipolar transistors (33 and 34) connected in a cascode circuit configuration and a second pair of bipolar transistors (35 and 36) connected in a cascode circuit configuration. In addition, the second push-pull amplifier circuit (41) has a first pair of bipolar transistors (43 and 44) connected in a cascode circuit configuration and a second pair of bipolar transistors (45 and 46) connected in a cascode circuit configuration. The channel distortion and gain response of the amplifier circuit (30) are significantly improved by the push-pull amplifier circuits (31 and 41).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.