High speed system for threshold matrix alignment and tiling, during creation of a binary half-tone image
US5781308A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Mar 4, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/4055
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system converts a source image into destination image pixels that are binary. The system includes a memory which stores at least a portion of a row of source grey level pixels, and a corresponding row of a threshold matrix of plural rows of grey level pixel values, each row including at least W pixel values. A scale register stores N source grey level pixel values that have been scaled to match N grey level destination image pixel locations. A threshold register outputs, in parallel, up to N of the W threshold pixel values. Alignment logic controllably enters the threshold pixel values into the threshold register. A controller operates the alignment logic to enter the W threshold pixel values into N contiguous storage positions in the threshold register, and if W greater than N, enables entry of excess ones of the W threshold pixel values into contiguous storage positions in the threshold register after the (W-N) previously entered threshold pixel values have been outputted. A comparator compares the N source pixel values with corresponding ones of the N threshold pixel values and assigns N binary values to the destination image in accordance with the comparing action.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.