Multiplier circuitry with improved storage and transfer of booth control coefficients
US5781462A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1995 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Sep 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is an object of the present invention to simplify a multiplier so as to reduce the circuit scale of a digital filter which uses a large number of multipliers. Outputs of a Booth decoder 4 are stored in registers 5.sub.1 -5.sub.(n+1)/2 provided corresponding to partial product generating circuits 106.sub.1 -106.sub.(n+1)2. By providing control signals from the registers 5.sub.1 -5.sub.(n+1)/2 to the partial product generating circuits 106.sub.1 -106.sub.(n+1)/2, the Booth decoder 4 is made common. The number of Booth decoders which have conventionally been provided in a one-to-one correspondence with the partial product generating circuits can be reduced to one and the multiplier can be simplified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.