Random access memory word line select circuit having rapid dynamic deselect
US5781497A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Aug 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A word line select circuit (10) having a rapid de-select operation is disclosed. A group of word lines (12a-12d) is selected in response to a row address and the initial edge of a timing signal (i/RAS) by pulling a group select node (24) to a low power supply voltage (Vss). A particular word line is selected by coupling one of the word line input driver nodes (16a-16d) to the group select node (24). The selected word line is driven to a pump voltage (Vpp) that is greater than the positive supply voltage (Vcc) by a word line driver circuit. Word lines are de-selected on the terminal edge of the i/RAS signal by simultaneously activating de-select transistors (18a-18d) coupled between each input driver node (16a-16d) and Vpp. In the preferred embodiment, the de-select operation also pre-charges the group select node (24) to Vcc-Vtn.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.