Cyclic redundancy coder
US5781566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Jun 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6569
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cyclic redundancy coder (10) is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a cyclic redundancy coding function. The cyclic redundancy coder (10) comprises a shift register (12) having a plurality of storage elements each for storing a bit of a cyclic redundancy code word. A tap register (16) stores a tap position indicator indicative of tap positions in the cyclic redundancy code word that are subject to a logical operation. An input (18) provides input data to the cyclic redundancy coder. A logic feedback network (20-28) receives the data from the input and provides the logical operation. The logic feedback network also provides a plurality of data bits generated in response to the input data and each bit contained in each storage element identified by the tap position indicator. The cyclic redundancy code word is produced by applying at least one of the plurality of data bits to one storage element that is adjacent a tap position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.