Synchronous digital transmission system having justification circuit that counts frame bytes, calculates offsets, compares thresholds, and initiates justification action
US5781597A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1995 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Feb 16, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/076
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A synchronous digital transmission system has network nodes each operating at a respective fixed internal clock rate, each with a justification device for adapting an incoming signal to the respective fixed internal clock rate thereof by positive or negative justification actions, and for controlling a memory device which stores payload bytes of a frame of the incoming signal and outputs the payload bytes at the internal clock rate of a respective network node. The justification device has a first circuit (10) for counting incoming/outgoing frame bytes and calculating at sampling instants (T.sub.i) a difference value (.DELTA..sub.i) and a change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i), has a second circuit (20) for calculating a control value (OFFSET) which is dependent on the change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i) and on a correction factor (LEAK), and has a third circuit (30) for comparing at the sampling instants (T.sub.i) the control value (OFFSET) with an upper threshold (U.sub.-- THRESH) and a lower threshold (L.sub.-- THRESH), and for initiating either a positive or negative justification action respec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.