Dynamic spare column replacement memory system
US5781717A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Sep 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An MxN dynamic spare column replacement memory system for storing M N-bit data words includes a random access memory (RAM) formed by a rectangular array of M rows and N+S columns of single-bit memory cells. Each row has a unique address and stores an N-bit word using a selected set of N of its N+S cells. An N-line parallel data bus provides data access to the DRAM. Responding to a switching instruction from a switch controller at the start of each memory access cycle, a crossbar switch selectively connects each of the N lines of the data bus to a separate one of the N+S columns. Thus during a memory read or write access cycle the N data lines access N cells of an addressed row columns. The remaining S cells of the row are unused. A host computer occasionally checks the DRAM for defective memory cells, and upon finding a defective cell or cells in any row, the host stores the row address and a switching instruction in the switch controller. At the beginning of each memory access cycle, the switch controller compares the DRAM address to its stored list of addresses of rows having a defective cell. If the current DRAM address matches a stored address, the switch controller switches da…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.