High speed communication bus
US5781745A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | May 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer network system containing a concentrator with a backplane that has a plurality of lines. The backplane contains data lines and control lines for managing and organizing the transfer of data between modules in the concentrator. The system contains intelligent devices that allow the selection of transmitting modules to occur at the same time as actual data transfer is going on between other modules. This is preferably done in a round robin arbitration process where, while data is being transferred by a first module, a bus arbitration device is placing addresses of modules which sequentially follow the transmitting module onto the control lines. Modules will see their address on the control lines, and if they have a packet to transmit, they then reserve the right to transmit after the presently transmitting module is finished. In this way the selection of the next module to transmit is performed in parallel, and does not slow down, the transfer of data between modules. The control lines are also able to indicate when a receiving module has been unable to copy a packet. The transmitting module can then resend the packet for either a maximum number of retries, or until the re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.