Memory system and method for selecting a different number of data channels depending on bus size
US5781918A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1996 |
| Grant date | Jul 14, 1998 |
| Priority date | — |
| Expiry date | Nov 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a main memory and a memory controller, the main memory including at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of cache FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.