Semiconductor package and lead frame
US5783861A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 10, 1997 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Mar 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises at least one semiconductor chip; a lead frame having a chip paddle supporting a semiconductor chip, a plurality of inner leads wire-bonded to the chip and a plurality of outer lead extended from the inner leads; and a plastic molding compound sealing the chip and the inner lead of the lead frame, wherein the outer leads of the lead frame being arranged within an area of a bottom surface of the plastic molding compound. A lead frame for use in the semiconductor package comprises a plurality of inner leads to be connected respectively to pads of a semiconductor chip; a plurality of outer leads extended from the inner lead and to be connected to other circuit, and the outer leads being bent to downward from an internal end of the inner lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.