CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods
US5784291A · kind A · utility
59Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Aug 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a single chip (102) that has a microprocessor (702), a memory controller unit (718), an internal bus (714) connecting the microprocessor (702) and the memory controller unit (718), and an external bus to internal bus interface circuit (716). The microprocessor (102) occupies a substantially rectangular region on a substrate (802). The memory controller unit (718) occupies a first strip along one side of the microprocessor unit (702) accessible via the bond pads broadside to the first strip. Other circuits, systems, and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.