Latched DRAM write bus for quickly clearing DRAM array with minimum power usage
US5784329A · kind A · utility
5Cited by
12References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1997 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Jan 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.