Method and system for implementing parity error recovery schemes in a data processing system
US5784394A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1996 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Nov 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus in a data processing system having a plurality of node controllers and a memory unit for each of the node controllers. Each one of the node controllers including at least one processor having a cache. Each memory unit including a plurality of entries each having an exclusive bit, an address tag, and an inclusion field. Each bit of the inclusion field representing one of the node controllers. The method and apparatus allow error recovery for errors occurring within the entries without using the ECC implementation. Specifically, two parity bits are used for detecting errors within an entry and logic for flushing any cache lines represented by the entry in error. The method and apparatus also includes means for detecting persistent errors and for indicating whether the error is generated by either hardware or software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.