Method for reducing the bandwidth requirement in a system including a video decoder and a video encoder
US5784571A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1995 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Dec 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a video system having an encoder and multiple decoders, a snooping circuit in each decoder compares an address on a common data bus to determine whether encoded video data is read or written by a host computer. When the address on the common data bus is detected to be an address within a predetermined range, the read or write data on the common data bus is latched into a first-in-first-out (FIFO) memory. A decoding circuit in each decoder decodes from the FIFO memory to provide a decoded video data output stream. In this manner, multiple decoders can be supported by the video system without additional bandwidth demand on the host computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.