Data processing system having memory controller for supplying current request and next request for access to the shared memory pipeline
US5784582A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1996 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Oct 28, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1615
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A router includes synchronous dynamic random access memory (SDRAM) based shared memory, with a controller configured to control the order in which the SDRAM access is granted to a plurality of interfaced components. In one embodiment, the controller's configuration minimizes the amount of time data from a particular source must wait to be read to and written from the SDRAM, and thus minimizes latency. In a different embodiment, the controller's configuration maximizes the amount of data read to and written from said SDRAM in a given amount of time and thus maximizes bandwidth. In yet another embodiment, characteristics of the latency minimization embodiment and the bandwidth maximization embodiment are combined to create a hybrid configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.