Multi-threaded FIFO pool buffer and bus transfer control system
US5784649A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1996 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Mar 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data tranfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.