Virtual to logical to physical address translation for distributed memory massively parallel processing systems
US5784706A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1993 |
| Grant date | Jul 21, 1998 |
| Priority date | — |
| Expiry date | Dec 13, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.