Semiconductor device and associated fabrication method
US5786273A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Feb 14, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/768
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.