Programmable digital frequency multiplier
US5786715A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Jun 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable digital frequency multiplier includes either a delay locked loop with an input clock or a ring oscillator which generates multiple phase delayed clock signals having a common frequency equal to that of the input clock and a corresponding number of equidistant phases. In the delay locked loop, a phase comparator compares the phase of the input clock as received by the first inverter circuit with the phase of the output of the last inverter circuit and generates an error signal which is used as a circuit bias control signal for each of the inverter circuits, thereby controlling the phase delay through each inverter circuit. The multiple inverter circuit output signals are individually gated in separate NOR gates with a corresponding number of frequency programming bits. The resulting NORed output signals are then processed together in an exclusive-NOR gate, thereby generating an output signal having a frequency which is an integer multiple of the input clock frequency with the integer multiple corresponding to the bit pattern of the frequency programming bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.