Voltage switching circuit for a semiconductor memory device
US5786723A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Jul 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a cascode circuit of the type having a first and second FET in a first leg and a third and fourth FET in a second leg comprising. The first and third FETs are switched between an on state and an off state substantially in tandem in response to a level change in an input signal to the cascode circuit. The second and fourth FETs are switched between an on state and an off state substantially in tandem in response to a level change in the input signal and substantially complimentary to the switching of said first and third FETS. A biasing signal is applied to a control electrode of the first FET responsive to transition of the input signal from a first level to a second level. A biasing signal is also applied to a control electrode of the third FET responsive to transition of the input signal from the second level to the first level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.