Control of body effect in MOS transistors by switching source-to-body bias
US5786724A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Dec 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M.sub.1, M.sub.2, M.sub.3 connected in parallel for respectively driving a capacitive load C.sub.L with a selected different voltage level V.sub.1, V.sub.2 or V.sub.3. Transistors M.sub.1, M.sub.2, M.sub.3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V.sub.1, V.sub.2 or V.sub.3 to charge the load CL. The largest voltage transistor M.sub.3 has its body connected to its source. The lower voltage transistors M.sub.1, M.sub.2 have their bodies respectively connected to switches S.sub.1, S.sub.2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V.sub.3 when the transistors are placed in the OFF condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.