Variable sample-rate DAC/ADC/converter system
US5786778A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1995 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Oct 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0657
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital oversampling noise-shaping system includes a digital noise-shaped clock signal generating circuit, including a DCO operating at a fixed master clock rate, that receives a digital input sample clock signal having an input sample rate and produces a noise-shaped clock signal having a variable rate with an average rate equal to a multiple of the input sample rate. In one embodiment, an interpolator is coupled to the clock signal generating circuit and receives the digital input samples at an input sample rate and, responsive to the noise-shaped clock signal, upsamples the digital input samples at the variable rate. A hold circuit repeats the interpolated samples at the master clock rate. A digital noise-shaping circuit, coupled to the hold circuit, performs digital noise-shaping on the repeated samples received from the hold circuit. In another embodiment, a decimator is coupled to the clock signal generating circuit. Digital input samples having an input sample rate are latched to the input of the decimator at a rate controlled by the noise-shaped clock signal. The clock signal generating circuit includes a PLL in one embodiment. The digital noise-shaping circuit, in one em…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.