Image processing system
US5786885A · kind A · utility
4Cited by
8References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 17, 1997 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Apr 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU 1 and card slots 3A to 3C are connected to one another through an interface circuit 2. The interface circuit 2 effects the selection of necessary card slots and the selective supply of read and write signals. The CPU 1, the interface circuit 2 and the card slots 3A to 3C are interconnected by the data and address buses for signal transmission and reception.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.