Low-power design techniques for high-performance CMOS circuits
US5787011A · kind A · utility
26Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1995 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Jan 19, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data processing circuit includes first and second signal paths, wherein the first signal path is a speed critical path. The first signal path includes a first logic gate (FIG. 22) for performing a predetermined logic operation, and the second signal path includes a second logic gate (FIG. 23) for performing the predetermined logic operation more slowly and with less power consumption than the first logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.