Method and apparatus for providing memory access in a processor pipeline
US5787026A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1995 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Dec 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a method and apparatus for providing operand reads in a processor pipeline. According to one aspect of the invention, a method is described for executing an instruction in a computer pipeline that requires different operands be read from the same register file in different stages of the computer pipeline. According to another aspect of the invention, a method is described for executing an instruction in a processor pipeline. According to this method, at least a first operand is read from a register file in a first stage of the processor pipeline. If execution of the instruction causes the processor to place the first operand in a storage area other than the register file, then the first operand in written to that storage area in a subsequent stage of the processor pipeline. Otherwise, one or more ALU operations are performed on the first operand and at least a second operand in a different subsequent stage of the processor pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.