Semiconductor memory device having a redundancy capability
US5787043A · kind A · utility
18Cited by
11References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1995 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Feb 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.