Multiprocessor computer backlane bus
US5787095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1997 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Mar 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer bus includes a first original signal line, a second redundant signal line, circuitry connected to the first original signal line and the second redundant signal line for driving the first original signal line and the second redundant signal line so as to convey on each identical information, circuitry for receiving signals on the first original signal line and the second redundant signal line, and error checking circuitry for comparing the signals on the first original signal line and the second redundant signal line and for indicating an error if the signals differ. By providing redundant signals for each signal that cannot be check with parity (for example wired-OR signals), the potential for single undetected points of failure is eliminated. In accordance with another embodiment of the invention, a computer having multiple modules connected by a backplane bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.