Internetworking device with enhanced protocol translation circuit
US5787255A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Apr 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A special memory overlay circuit uses a first DRAM buffer memory in combination with a second faster SRAM buffer memory to reduce the time required to translate information into different network protocols. Packet data is stored in the DRAM buffer memory and packet headers requiring manipulation are stored in the SRAM buffer memory. Because the SRAM has a faster data access time than the DRAM buffer memory, a processor can reformat the packet header into different network protocols in a shorter amount of time. Packet headers also use a relatively small amount of memory compared to remaining packet data. Since the SRAM buffer memory is only used for storing packet headers, relatively little additional cost is required to utilize the faster SRAM memory while substantially increasing network performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.