Bus arbitration system having a pair of logic networks to control data transfer between a memory and a pair of buses
US5787265A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer/disk storage system is provided for enabling data to be transferred between a memory and either one of a pair of buses. The system includes a pair of logic networks. The first logic network is adapted to enable data to be transferred between the memory and a first one of the buses in response to a first bus availability signal. The first logic network also provides a second bus availability signal indicating when the memory is available to transfer data between such memory and the second one of the buses. A second logic network is adapted to enable data to be transferred between the memory and the second one of the buses in response to the second bus availability signal. The second logic network also provides the first bus availability signal indicating when the memory is available to transfer data between such memory and the second one of the buses. A clock pulse generator is provided having a pair of oscillators and a network for producing clock pulses on an output of the pulse generator from one of the pair of oscillators and when such one of the pair of oscillators becomes defective, producing such clock pulses on such output from the other one of the pair of oscilla…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.