Computer system with a cache coherent non-uniform memory access architecture using a fast tag cache to accelerate memory references
US5787468A · kind A · utility
12Cited by
2References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Jun 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast tag cache is an array to cache a limited set of identifiers specifying the residency and access rights to memory blocks and cache blocks contained in a node within a distributed memory system built using a cache coherent non-uniform memory access architecture. The purpose of the fast tag array is to ensure peak processor-memory bus throughput each node and minimize the amount of memory required to hold cache state information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.