Bus protocol for locked cycle cache hit
US5787486A · kind A · utility
68Cited by
16References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for maintaining lock characteristics while providing selective access to a cache during lock cycles. To guarantee that only one master accesses memory at a time, locked cycles are always passed to the internal arbitration unit of the memory controller, even if they are cache hits. If the local bus is not granted or cannot be guaranteed that it will be granted the bus for the locked cycle, the cycle is cancelled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.