Fabrication of metal-ferroelectric-metal capacitors with a two step patterning sequence
US5789323A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Apr 25, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
Abstract
A method of fabricating a metal-ferroelectric-metal ("MFM") capacitor includes the steps of depositing a silicon dioxide layer on a silicon or other substrate, a lower platinum or other noble metal electrode, a PZT or other ferroelectric material dielectric layer, and an upper platinum or other noble metal electrode. The upper electrode and ferroelectric dielectric layer are patterned and etched according to a first pattern corresponding to the final dimensions of the ferroelectric dielectric layer. The upper electrode and lower electrode are subsequently patterned and etched according to a second pattern corresponding to the final dimensions of one or more upper electrodes and the final extent of the lower electrode. The second etching step leaves a benign vestigial upper electrode feature. An oxide layer is finally deposited over the entire surface of the MFM capacitor structure, which is etched and metalized over desired upper and lower electrode contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.