Non-volatile memory having multi-bit data cells with double layered floating gate structure
US5789777A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 2, 1997 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Jan 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5613
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The non-volatile memory has a storage cell complying with multi-bit data by means of a double layered floating gate architecture. The cell comprises: source 2 and drain 3 which are distant from each other along a direction L in a semiconductor substrate 1; a single first floating gate 4A which is provided between the source and the drain and above a principal plane of the semiconductor substrate and extends along a direction crossing the direction L; a control gate 5 which is placed between the drain ad source and above a principal plane of the first floating gate; high impurity concentration layers 21, 22 which are isolated from the source and drain in the semiconductor substrate; a plurality of second floating gates 4B.sub.1, 4B.sub.2 which respectively extend across the first floating gate and above a principal plane of the first floating gate and extend from a position different than either of the source and the drain up to a position above a principal plane of the high impurity concentration layer; and a plurality of program gates 6.sub.1, 6.sub.2 which are placed correspondingly above principal planes of the second floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.