Semiconductor cap
US5789810A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Dec 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a cap for use in a semiconductor package is disclosed. The semiconductor package includes a semiconductor chip and a substrate. The chip is mounted with the substrate at a chip locus. The method preferably comprises the steps of placing a slug in a die, and exercising the die to cold flow the slug to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperating with the base to establish a well bounded by the walls and the base. The walls terminate in a plane, and the well clears the chip when the cap is mounted on the substrate at the chip locus. The invention further includes a cap for use in a semiconductor package. The cap comprises a structure cold flowed from a slug in a die to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperates with the polygonal base to establish a well bounded by the plurality of walls and the polygonal base. The walls terminate generally in a termination plane, and the well clears the chip when the cap is abuttingly mounted at the termination …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.