ECL level/CMOS level logic signal interfacing device
US5789941A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1997 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Feb 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An ECL level/CMOS level logic signal interfacing device includes, connected in cascade, a circuit for generating an in-phase relationship with an ECL level input signal, a threshold inverter circuit receiving the in-phase signal at an inverter input and delivering an inverted in-phase signal, a shaping inverter circuit receiving the inverted in-phase signal and outputting a calibrated in-phase signal, and an output amplifier circuit receiving the calibrated in-phase signal and outputting an output signal to the CMOS level in phase relationship with the ECL level input signal. The circuits are supplied with a CMOS level supply voltage relative to a reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.