D flip-flop having asynchronous data loading
US5789957A · kind A · utility
6Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Aug 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.