Calibrating the DC-offset of amplifiers
US5789974A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Jul 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45048
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The dc-offset voltage of an amplifier is calibrated by: (1) configuring the amplifier as a comparator, (2) using the output of the comparator to drive the up/down select input of an up/down counter, and (3) using the output count of the up/down counter to control: (a) a dc-offset correction voltage being: (i) applied across the inputs of the amplifier, or (ii) being used to adjust a voltage which controls an operating parameter of a device in the amplifier, or (b) switches which selectively adjust the effective size or operating conditions of a transistor or other device such that the dc-offset voltage of the amplifier is adjusted corresponding to the value of the output count. At the end of a calibration cycle, the output count of the up/down counter is maintained and is used to: (a) control a voltage which is applied permanently in series with one of the inputs of the amplifier or to an operating parameter control lead of a device in the amplifier, or (b) maintain the position of switches used to adjust the effective size or operating conditions of the transistor or other device in the amplifier to compensate for the offset voltage thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.