FSK modulating and demodulating apparatus wherein each binary data is represented by same number of cycles of modulated signal
US5789991A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Dec 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/156
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal FSK-modulated with a binary data signal has first signal portions representing first logical level data contained in the binary data signal and second signal portions representing second logical level data contained in the binary data signal. Each of the first signal portions has a first frequency and lasts for a first time period and each of the second signal portions has a second frequency and lasts for a second time period. These first and second time periods are determined such that a number of cycles of the FSK-modulated signal appearing in each of the first time periods is equal to a number of cycles of the FSK-modulated signal appearing in each of the second time periods. For demodulation of the FSK-modulated signal, a time period corresponding to a predetermined number of successively appearing cycles of the modulated signal, among those appearing during the whole of each signal portion, is established, clock pulses from a clock pulse source are counted for the established time period, and the resulting count values are compared to determine whether received data is a first logical level data or second logical level data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.