Error variance processing equipment for display device
US5790095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Oct 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0266
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Coupled to an error variance circuit 11 is an emission luminance characteristic acquisition circuit 20 that counts up, at a display number counter 21, the display number in the single or plural frames of the respective bits of image data by the counters, M in number, corresponding to said bits, then solves for display area percentage (Sk) dividing, at a display area percentage operation part 22, the display dot number as counted at a display number counter 21, by total dot number, and acquires the luminance deviation characteristic for each bit by means of an emission luminance deviation characteristic measuring part 24. The luminance deviation thus obtained is renewed for each frame and transferred to the error variance circuit 11, and processed for error variance on the basis of the emission luminance characteristic to be output at PDP. At low level, on the other hand, the luminance deviation is rendered either fixed type luminance deviation or emission luminance level more or less higher than the actual one to reduce the diffusion noise particularly at the low level image portion thereby obtaining a more natural image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.