System and method for using a frame buffer in cached mode to increase bus utilization during graphics operations
US5790137A · kind A · utility
14Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Oct 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for increasing utilization of a system bus and frame buffer throughput in a graphic display system. The frame buffer is changed from cache inhibited mode to cached mode in order to take advantage of the burst mode of system bus in which a plurality of values are transferred to the frame buffer following one address. Data coherency is maintained between the cache and the frame buffer by invalidating a cache-line before writing to the cache-line, and by explicitly flushing the cache-line after the cache-line is filled with data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.