Horizontal synchronization signal stabilization method and apparatus
US5790200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An arrangement for stabilizing a horizontal synchronization signal, serving as an input signal for a phase-locked loop (PLL) for generating a clock signal, by separating the horizontal synchronization signal from a composite synchronization signal including both horizontal and vertical synchronization signals. A horizontal synchronization gate signal is generated for outputting a pulse signal approximately in phase with the horizontal synchronization signal and having at least the pulse width of the horizontal synchronization signal in accordance with the composite synchronization signal and a clock pulse signal having a predetermined frequency. The horizontal synchronization signal is retrieved from the composite synchronization signal in accordance with a logical product when matching the polarity of the horizontal synchronization gate signal with the polarity of the composite synchronization signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.